《混合信号晶片模拟、验证软件》(Dolphin Integration Smash)v5.16.1

中文名: 混合信号晶片模拟、验证软件
英文名: Dolphin Integration Smash
资源格式: 压缩包
版本: v5.16.1
发行时间: 2010年
制作发行: Dolphin Integration
地区: 法国
语言: 英文
简介: 




Smash 为法国Dolphin Integration公司所发展之混合信号兼顾多层次模拟软体， 能完全符合混合类比与逻辑讯号电路的需求。混合讯号指的是Smash能处理类比或是连续时间的讯号与不连续时间的讯号，例如: 逻辑(二进制binary)或数位(十进制decimal)。多层次指的是Smash 并没有被限制在某些modeling level 上，即Smash 能处理电晶体层次、闸阶层次、功能层次、行为层次并与来自于类比与逻辑的子电路加以混合模拟。意味着Smash可用在任何层次上的设计作一些精确的电路修正，这表示你将能轻易处理任何复杂性的电路。另外Smash 有强大的多语言功能，能与SPICE、Verilog-HDL、VHDL、ABCD(C-language)与VHDL-AMS相容，可以将类比区块以SPICE 语法描述与数位区块以Verilog-HDL 语法或VHDL 语法描述的设计作多层次混合信号模拟。 Smash 能快速地模拟验证所设计的混合信号晶片，非常适合用来解决混合信号晶片设计问题，以提供高效能的混合信号晶片设计模拟验证环境，减化复杂电路模拟验证的程式，缩短晶片设计的时程。

SMASH Vision
Mixed-Signal Multi-Level & Multi-Domain Simulation
Missing EDA Links University Program
A specific approach for universities
Give your students the opportunity to get acquainted with state-of-the-art mixed-signal design solutions!
Thanks to Dolphin Integration EDA solutions, enjoy getting acquainted with the intricacies of logic, analog and mixed-signal modeling enabled by multi-language simulation!
State-of-the-art analog and mixed-signal design requires analysis capabilities allowing to automate and secure multiple design steps while simplifying the investigation and debug of mixed-language designs. While the circuit browser gives direct access to instances and models in the netlist, error and warning messages issued by SMASH now contain clickable file and line number information for efficient debugging.
SMASH 5.16 delivers new analyses dedicated to analog design, along with Verilog/Verilog-A behavioral improvements both for logic testbenches and for analog modeling.Key enhancements
Increased analog design productivity with linear loop stability (.LSTB) and data sampling noise (.SAMPLE) analyses
Improved compliance with Verilog standards for testbench descriptions
Increased Verilog-A simulation performance including support of analog functions for behavioral modeling
Extended HSPICE compliance with the support of .ALTER and .DEL LIB directives
Enhanced debugging capabilities with direct access to analog ports in the “circuit” pane
Improved device analysis capabilities with interactive editing of SPICE device parameters and drawing of device characteristics
Description of the benefits
Verilog compliance enhancements target testbench descriptions with access to signals and variables using hierarchical names and system tasks for file access in read mode.
Verilog-A improvements include additional capabilities for behavioral modeling, with user defined analog functions and string parameters for modules, as well as increased simulation performance, more specifically for Compact Models.
Error, warning and information messages issued during the parsing of SPICE descriptions have been significantly enhanced in order to provide the designer with more easily exploitable messages with explicit file and line number information. The file and line number in the message is interpreted by SMASH as an active link which allows to quickly locate the origin of problems simply by clicking on the link in the report.
The “circuit” browser has been extended to provide quick access to the source level description of instances and models directly from the user interface of SMASH.
Highlight
Don’t miss out discovering the new “ICD – Interactive Curve Display” solution for waveform viewing.